A FPGA Based Forth Microprocessor

Systems which employ a microprocessor together with an application speci c FPGA based coprocessor are common today. These applications can reduce power consumption and system costs by incorporating the microprocessor in the FPGA. For such applications, a microprocessor which has good performance, occupies a minimal amount of FPGA resources, has a good high level language software development environment and good code density is desirable. In this paper a 16 bit FPGA based microprocessor, called MSL16, optimised for such applications is described. MSL16 utilises a stack architecture with each instruction occupying only 4 bits, leading to a small instruction set, simple datapath and control, and high code density. MSL16 was speci cally designed to e ciently execute the programming language \Forth". The Forth language has the desirable features of portability and high code density, and it is well suited to control, DSP, real{time and embedded applications. The architecture for MSL16 is similar to that of the MuP21 [2]. The MuP21 is a 20 bit CPU which has 25 5{bit instructions and implemented in 1.2 micron CMOS process, uses 7000 CMOS transistors and has a peak execution rate of 100 MIPS. Compared with the MuP21, the MSL16 architecture has 16 4{ bit instructions, and when implemented using a Xilinx Inc, 4000 series FPGA, occupies 175 con gurable logic blocks (CLBs) at a peak clock frequency of 33 MHz on a 4006E{1 device (i.e. a peak execution rate of 33 MIPS). The datapath of MSL16 is shown in Figure 1. MSL16 is a 2 stack machine with 16 bit data and memory buses. The data stack is used for temporary variable storage and subroutine parameter passing, and the return stack is used mainly to hold subroutine return addresses. The data and return stack are implemented internally on the FPGA which allows them to be accessed in parallel with instruction fetches on the memory bus. A two stage FETCH/EXECUTE pipeline is employed. Instructions involving a memory reference (@ and !), change the ow of execution, (CALL and GOTO) and SWAP take two cycles and the remaining instructions are single cycle. The main components in the datapath of MSL16 are a 16 deep data stack (DS) for temporary variables and subroutine parameters; the T register which holds the very top element of the stack so that the top two stack elements are available to the ALU simultaneously; a 16 deep return stack (RS) to store subroutine return addresses; an instruction register (IR) which holds the four 4-bit instructions to be executed; a PC (Program Counter) which stores the address of the next instruction; an IR (Instruction Register) which stores the address of the next instruction; and an ALU which takes operands from T and the top element of either DS or RS and returns the result to T.